Semiconductor devices using metal-semiconductor barriers (referred to as Schottky barriers) instead of p-n junctions have been developed to convert incident light into electrical energy. Silicon is often used as the semiconductor material in Schottky barrier photodetectors operating in the IR portion of the electromagnetic energy spectrum. In its most conventional form, a silicon-based Schottky barrier photodiode consists of a thin metallic film (such as a silicide film) disposed on a silicon layer. Incident light is applied perpendicular to (i.e., “normal to”) this structure, passing through the relatively thin metallic film, where the thin film absorbs only a portion of the light, thus resulting in extremely low external quantum efficiency levels. As a result, conventional “normal incidence” photodetectors require a relatively large active detection area in order to collect a sufficient amount of optical energy to function properly. However, as the detection area increases, the dark current (unwanted noise signal) increases as well. Moreover, while relatively simple in structure, such normal incidence detectors typically require cooling, again associated with a relatively high dark current value.
Improvements in optical absorption and quantum efficiency in silicon-based Schottky barrier photodetectors have been the source of much investigation over the years. In one case, the optical absorption has been improved by inducing a surface plasmon mode at the metal-semiconductor interface, as disclosed in U.S. Pat. No. 5,685,919 issued to K. Saito et al. on Nov. 11, 1997. In this arrangement, a semicylindrical lens is disposed over the metallic layer and used to re-orient the incoming light from normal incidence to an angle associated with creating the surface plasmon layer. U.S. Pat. No. 4,857,973, issued to A. C. Yang et al. on Aug. 15, 1989 discloses an alternative Schottky barrier photodetector arrangement, where the photodetector is monolithically integrated with a single crystal silicon rib waveguide and positioned to absorb the “tail” of the optical signal as it passes along the rib waveguide underneath a silicide layer. While an improvement in absorption efficiency may be achieved with the Yang et al. structure, significant losses remain in terms of scattering losses along the sidewalls of the rib waveguide structure inasmuch as the rib is created by partially removing portions of a relatively thick silicon layer. Moreover, significant difficulties remain in terms of controlling the dimensions (particularly the height), as well as the smoothness, of such a rib waveguide structure. Indeed, the implementation of a “rib” structure (particularly with sub-micron dimensions) is extremely difficult with CMOS-based conventional processing technologies. Further, the non-planar geometry of the Yang et al. structure is not considered as a preferred arrangement from a manufacturing point of view, particularly in terms of the reliability and robustness of the design.
An exemplary prior art silicon-based photodetector that is compatible with conventional CMOS processing is described in U.S. Pat. No. 7,358,585, issued to V. Patel et al. on Apr. 15, 2008 and assigned to the assignee of this application. In the Patel et al. structure, a silicide layer (or other appropriate metallic layer) is disposed over a planar silicon waveguide layer formed as a sub-micron thick surface layer of a “silicon-on-insulator” (SOT) structure (this sub-micron surface waveguide layer often referred to in the art as the “SOT layer”). Ohmic contacts are applied to both the planar SOT layer of the SOT structure and the silicide layer. An optical signal propagating laterally along the optical waveguide within the planar SOT layer will thus pass under the silicide layer, where the “tail” of the optical energy will intercept the silicide and be converted into electrical energy. Since the arrangement of Patel et al. is based on implementing a silicide detector on a planar silicon surface and does not require the formation of a single crystal silicon rib waveguide, significant improvements in efficiency over the structure of Yang et al. can be realized, while also being compatible with conventional planar CMOS processing technologies.
While considered to be an advance over existing devices, the planar, waveguide-based structure of Patel et al. has been found to be somewhat limited in its responsivity, associated with the inherent properties of the silicide material itself. Inasmuch as silicide detectors were initially designed for use in power monitoring applications, responsivity and processing simplicity were not the concerns that they are today.
Thus, a need remains for a high speed silicon-based detector that remains compatible with standard CMOS processing, yet provides the responsivity required for use as a power monitor or feedback detector in high speed systems.